Infrared imagers are used in a large number of applications. Infrared imagers generally include an array of pixels. One limitation on the cost of producing infrared imagers is the pixel size. In general, a smaller pixel size allows the imager chip to have smaller dimensions, and thus a lower cost. However, previous manufacturing techniques for infrared imagers based on thermopiles as infrared sensing structures have been too imprecise to produce smaller pixels, for example, pixels with dimensions under 120 μm.
Imaging devices using thermopiles as sensing structures may include a thermopile structure suspended over a cavity in a semiconductor substrate, where a dielectric membrane of the thermopile has openings through to the cavity. Prior manufacturing methods have been challenged in ensuring the proper shape of the cavity under the membrane as well as a much higher precision in aligning this cavity with the position of the thermopile pixel. These features are especially needed when fabricating thermopile pixels which are smaller in size (for example, 120 μm or smaller).
The previous method of releasing the membrane for the thermopile pixels was based on anisotropic etching from the back of the membrane, for example, using deep reactive ion etching (DRIE). However, DRIE is generally not precise enough to ensure the correct positioning of the cavity under the membrane. The previous methods are typically limited to precision rates of +/−5 μm.
Another method involves wet anisotropic etching of the semiconductor substrate through openings in the membrane. While this method provides good control of the position and shape of the cavity relative to the position and shape of the membrane, the aggressive etchants used, for example, tetramethyl ammonium hydroxide (TMAH) etchant, are highly aggressive and will attack other structures present on the wafer, making the method unsuitable for integration with CMOS.
Dry isotropic etchants on the other hand, for example, xenon fluoride (XeF2) is highly selective and will not attack other structures present on the wafer, making it suitable for integration with CMOS. Unfortunately, isotropic etching is unsuitable for etching deep cavities in the semiconductor substrate through openings in the membrane due to difficulties producing square/rectangular cavity shapes.
Other issues with the prior manufacturing methods include a relatively slow release of the membrane, and a relatively high consumption of C4F8. Therefore, there is a need in the industry to improve one or more of the abovementioned deficiencies.